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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">PMZR_EL0, Performance Monitors Zero with Mask</h1><p>The PMZR_EL0 characteristics are:</p><h2>Purpose</h2>
        <p>Zero the set of counters specified by the mask written to PMZR_EL0.</p>
      <h2>Configuration</h2><p>AArch64 System register PMZR_EL0 bits [63:0] are architecturally mapped to External register <a href="pmu.pmzr_el0.html">PMU.PMZR_EL0[63:0]</a> when FEAT_PMUv3_EXT64 is implemented and FEAT_PMUv3p9 is implemented.</p><p>This register is present only when FEAT_PMUv3p9 is implemented. Otherwise, direct accesses to PMZR_EL0 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>PMZR_EL0 is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="31"><a href="#fieldset_0-63_33">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-32_32-1">F0</a></td></tr><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31">C</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P30</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P29</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P28</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P27</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P26</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P25</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P24</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P23</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P22</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P21</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P20</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P19</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P18</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P17</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P16</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P15</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P14</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P13</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P12</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P11</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P10</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P9</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P8</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P7</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P6</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P5</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P4</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P3</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P0</a></td></tr></tbody></table><h4 id="fieldset_0-63_33">Bits [63:33]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-32_32-1">F&lt;m&gt;, bit [m+32], for m = 0<span class="condition"><br/>When FEAT_PMUv3_ICNTR is implemented:
                        </span></h4><div class="field">
      <p>Zero fixed-function counter &lt;m&gt;.</p>
    <table class="valuetable"><tr><th>F&lt;m&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Write is ignored.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Set fixed-function counter &lt;m&gt; to zero.</p>
        </td></tr></table><p>Writing 1 to PMZR_EL0.F0 sets <a href="AArch64-pmicntr_el0.html">PMICNTR_EL0</a> to zero.</p>
<ul>
<li>This field ignores writes if any of the following are true:<ul>
<li>All of the following are true:<ul>
<li><a href="AArch64-pmuserenr_el0.html">PMUSERENR_EL0</a>.UEN == 0 or <a href="AArch64-pmuacr_el1.html">PMUACR_EL1</a>.F&lt;m&gt; == 0.
</li><li>Accessed at EL0.
</li></ul>

</li><li>All of the following are true:<ul>
<li>EL3 is implemented.
</li><li><a href="AArch64-mdcr_el3.html">MDCR_EL3</a>.EnPM2 == 0.
</li><li>Accessed at EL2, EL1, or EL0.
</li></ul>

</li><li>All of the following are true:<ul>
<li><span class="xref">FEAT_FGT2</span> is implemented.
</li><li><a href="AArch64-hdfgwtr2_el2.html">HDFGWTR2_EL2</a>.nPMICFILTR_EL0 == 0.
</li><li>EL2 is implemented and enabled in the current Security state.
</li><li>Accessed at EL1 or EL0.
</li><li><a href="AArch64-hcr_el2.html">HCR_EL2</a>.{E2H,TGE} != {1,1}.
</li></ul>

</li><li>All of the following are true:<ul>
<li>Accessed at EL0.
</li><li><a href="AArch64-pmuserenr_el0.html">PMUSERENR_EL0</a>.IR == 1.
</li></ul>

</li></ul>

</li><li>Otherwise access to this field is WO.
</li></ul></div><h4 id="fieldset_0-32_32-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-31_31">C, bit [31]</h4><div class="field">
      <p>Zero <a href="AArch64-pmccntr_el0.html">PMCCNTR_EL0</a>.</p>
    <table class="valuetable"><tr><th>C</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Write is ignored.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Set <a href="AArch64-pmccntr_el0.html">PMCCNTR_EL0</a> to zero.</p>
        </td></tr></table><p>Accessing this field has the following behavior:</p>
<ul>
<li>This field ignores writes if any of the following are true:<ul>
<li>All of the following are true:<ul>
<li>Accessed at EL0.
</li><li><a href="AArch64-pmuserenr_el0.html">PMUSERENR_EL0</a>.UEN == 1.
</li><li><a href="AArch64-pmuacr_el1.html">PMUACR_EL1</a>.C == 0.
</li></ul>

</li><li>All of the following are true:<ul>
<li>Accessed at EL0.
</li><li><a href="AArch64-pmuserenr_el0.html">PMUSERENR_EL0</a>.{UEN,CR} == {1,1}.
</li></ul>

</li></ul>

</li><li>Otherwise access to this field is WO.
</li></ul></div><h4 id="fieldset_0-30_0">P&lt;m&gt;, bit [m], for m = 30 to 0</h4><div class="field">
      <p>Zero <a href="AArch64-pmevcntrn_el0.html">PMEVCNTR&lt;m&gt;_EL0</a>.</p>
    <table class="valuetable"><tr><th>P&lt;m&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Write is ignored.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Set <a href="AArch64-pmevcntrn_el0.html">PMEVCNTR&lt;m&gt;_EL0</a> to zero.</p>
        </td></tr></table><p>Accessing this field has the following behavior:</p>
<ul>
<li>This field ignores writes if any of the following are true:<ul>
<li>All of the following are true:<ul>
<li>Accessed at EL0.
</li><li><a href="AArch64-pmuserenr_el0.html">PMUSERENR_EL0</a>.UEN == 1.
</li><li><a href="AArch64-pmuacr_el1.html">PMUACR_EL1</a>.P&lt;m&gt; == 0.
</li></ul>

</li><li>All of the following are true:<ul>
<li>Accessed at EL0.
</li><li><a href="AArch64-pmuserenr_el0.html">PMUSERENR_EL0</a>.{UEN,ER} == {1,1}.
</li></ul>

</li><li>All of the following are true:<ul>
<li>EL2 is implemented and enabled in the current Security state.
</li><li>m &gt;= UInt(<a href="AArch64-mdcr_el2.html">MDCR_EL2</a>.HPMN).
</li><li>Accessed at EL0 or EL1.
</li></ul>

</li><li>m &gt;= UInt(<a href="AArch64-pmcr_el0.html">PMCR_EL0</a>.N).
</li></ul>

</li><li>Otherwise access to this field is W1C.
</li></ul></div><div class="access_mechanisms"><h2>Accessing PMZR_EL0</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MSR PMZR_EL0, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b011</td><td>0b1001</td><td>0b1101</td><td>0b100</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; MDCR_EL3.TPM == '1' then
        UNDEFINED;
    elsif (IsFeatureImplemented(FEAT_PMUv3p9) &amp;&amp; PMUSERENR_EL0.&lt;UEN,EN&gt; == '00') || (!IsFeatureImplemented(FEAT_PMUv3p9) &amp;&amp; PMUSERENR_EL0.EN == '0') then
        if EL2Enabled() &amp;&amp; HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x18);
        else
            AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; != '11' &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; HaveEL(EL3) &amp;&amp; SCR_EL3.FGTEn2 == '0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; != '11' &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; HDFGWTR2_EL2.nPMZR_EL0 == '0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; MDCR_EL2.TPM == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3.TPM == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        PMZR_EL0 = X[t, 64];
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; MDCR_EL3.TPM == '1' then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; HaveEL(EL3) &amp;&amp; SCR_EL3.FGTEn2 == '0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; HDFGWTR2_EL2.nPMZR_EL0 == '0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; MDCR_EL2.TPM == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3.TPM == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        PMZR_EL0 = X[t, 64];
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; MDCR_EL3.TPM == '1' then
        UNDEFINED;
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3.TPM == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        PMZR_EL0 = X[t, 64];
elsif PSTATE.EL == EL3 then
    PMZR_EL0 = X[t, 64];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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